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Q4) louimas loHimax) Qs U Vmin) Viimas) The circult diagram of a TTL NAND gate is illustrated with a set of parameters:- Vec 16 mA R R2 R -0.4 mA 4k2 1.6 kn 130 (max) = -1.6 mA lon(max= 50 μΑ 2.0 V 0.8 V Vollmay=0.4 V Ds х VoHimin=2.0 V 13 ns D 9 ns Q4 1 ns 1.5 ns RS 1 ko 2 mA 11 B tphlity) test) trum) trutora Icchappel 1 1 ond 1 (0) (ii) The gate contains a circuit referred to as a totem pole. What components in the above circuit make up the totem pole? (4 marks) What are the status of Q1, Q2, Q3 and Q4 when input A and B are both in logic high? For full marks your answer should give estimates of the associated node voltages. (10 marks) If 3 of the above gates are connected in series (with the two inputs of each gate connected together), determine the overall typical propagation delay teltyp). (6 marks) (ili) Notes Со