Answer Happy

Problem: Consider the ALU example from Unit 8 (pages 57-58). a) Use Verilog behavioral modeling to model each component separately i.e. adder, MUX, etc. and then instantiate these components to model the whole ALU. b) Write a Verilog test bench to test your design and verify its correctness by simulation. Show snapshots of your simulation to demonstrate its correctness. For each function, test at least 2 input combinations of your choice to demonstrate correct functionality. Deliverables: Your report (Word or PDF) should contain: - Circuit design - Verilog modules and test benches (link to your code in EDAPlayground) - The timing diagrams (waveforms) taken directly as snapshots from the simulator. Have as many snapshots as needed to cover all the test cases.

Arithmetic and Logic Unit (ALU) ALU performs arithmetic and logic functions A[n-1:0] : B[n-1:0) n F[2:0] + ALU * We will design an ALU with 8 functions VC n The function F is coded with 3 bits as follows: R [n-1:0) ALU Result R = A + B Function F = 000 (ADD) F = 001 (ADD + 1) F = 010 (SUB - 1) F = 011 (SUB) R = A + B + 1 Function F = 100 (AND) F = 101 (OR) F = 110 (NOR) F = 111 (XOR) ALU Result R=A&B REAB R = n(AB) R = (A^B) R = A-B-1 R=A-B

A[n-1:0] B[n-1:0) F[2:0) = 3-bit Function code Fi n n n n XOR gates n AND gates n OR gates n XOR gates Cn. 1 n-bit Adder comFo Cn nnn 1 2 3 mux 0 -S1 So = F F Fo V = Overflow C = Carry output 0 1 mux st-F2 VC n ** Result = R(n-1:0) [1 =