Answer Happy

Problem 2
In Part 1, you have encountered this
circuit, where the serial output So of a 5-
bit load/shift register is used to enable a
mod-N counter. When Load = 1, the
register is loaded with the values on
D4..D0 while the counter is loaded with 0
(cleared).
a. Write the verilog code for the load/ shift register in
HDLBits.
b. Write the verilog code for the mod-N counter in HDLBits.
c. Write the verilog code for the top module in HDLBits,
with one instance of the load/shift register and one instance of
the mod-N counter.
d. Run the simulation, using the following testbench
template to help you start. Capture its waveform.
use the testbench
module testbench ();
reg Clk=0;
always #5 Clk = ~Clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(Clk); // Probe signal "Clk"
// A testbench
reg Load = 1’b0;
reg [4:0] D;
wire [2:0] Q;
initial begin // follow the given timing diagram
#10 Load = 1’b1; D = 5’b10110; // apply a Load pulse
#10 Load = 1’b0;
#50; // run a few clock cycles
$display ("Hello world! The current time is (%0d ps)",
$time);
#10 $finish; // Quit the simulation
end
top DUT ( .Clk(Clk), .Load(Load), .D(D ), .Q(Q) ); //
Sub-modules work too.
endmodule
module top (input Clk, input Load, input [4:0] D, output [2:0]
Q);
// declare internal wires
// instantiate load/shift register
// instantiate mod-N counter
`probe(Load); // Sub-modules can also have `probe()
`probe(D);
`probe(Q);
endmodule // top
// module for load/shift register
// module for mod-N counter
All tied to os o D4D3D2D1Do 1 0 1 1 0 Load 5 bit load/shift register Load So Si mod-N counter Enable Qs Load Q outputs X ها ساده ابراه D4 Ds D3 CIK D2 Di Do CIK Clk 1