Assume a 5 mW max power for the pre-lab section.
Posted: Sat May 21, 2022 12:32 am
Assume a 5 mW max power for the pre-lab section.
Pre-Lab: 1- Design a Common Gate stage with a gain of 5 and an input impedance = 50 Ohms. Assume Vov = 0.1 V, VDD = 1.8V. Assume a voltage divider biasing, this means you need to find RS, RD, R1 and R2 as well as the (W/L) ratio. 2- Design a Source Follower with a gain of 0.6 for an RL = 100 Ohms, and an Input impedance of 100KOhms. Assume a simple biasing structure using an RG and a VDD = 1.8V. Assume kp = 100 UA/V2, VTH = 0.4V, and Lambda = 0 =
Pre-Lab: 1- Design a Common Gate stage with a gain of 5 and an input impedance = 50 Ohms. Assume Vov = 0.1 V, VDD = 1.8V. Assume a voltage divider biasing, this means you need to find RS, RD, R1 and R2 as well as the (W/L) ratio. 2- Design a Source Follower with a gain of 0.6 for an RL = 100 Ohms, and an Input impedance of 100KOhms. Assume a simple biasing structure using an RG and a VDD = 1.8V. Assume kp = 100 UA/V2, VTH = 0.4V, and Lambda = 0 =