Answer Happy

5. (15 Points ) DC Analysis Consider the following sequential circuit with 3 edge-triggered flip-flops and some logic gates. Assume that tsu= 3 ns, thold = 2 ns, and tc2q = 1 ns. a) Identify the critical path on the schematic. b) What is the maximum operating clock frequency? c) Identify the path with hold time violation on the schematic. d) How do you modify the circuit to avoid the hold time violation without any penalty on the operating frequency? a) 5oops 500 ps DQ 750 ps 350 ps 350 ps 500 ps ID Q! 150 ps ID Q! 150 ps 150 ps Clock Figure 4 Sequential circuit