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Question 3 Answer the following questions about sequential circuits. (a) What is the minimum number of flip-flops required to implement a clock divider that generates a 25 MHz clock from a 200 MHz clock? (2 marks) (b) What are the value of registers a, b and c after the positive edge of the clock? Explain why. module Q3b (a, d, clk) input d; output a; reg a, b, c; always @ (posedge clk) begin C = d; b = c; a = b; end endmodule (4 marks) (c) Each block shown in Figure 2 has the following propagation delays: Logic 1 (2ns), Logic 2 (5ns), Logic 3 (8 ns), Logic 3 (4 ns), multiplexer (1 ns) and Flip-flops (1ns). What is the maximum clock frequency for the design given in Figure 2? If the output is a function of both INPUT1 and INPUT2, how long does it take the first correct OUTPUT to be generated at the output? INPUT CLK LOGIC 2 INPUT1 LOGIC 1 LOGIC 3 CLK CLK LOGIC 4 OUTPUT CLK Figure 2 (6 marks)