Answer Happy

For what binary value will the first match occur
[ Select ]
["00100", "00011", "00001", "01111"] , in which
pipeline stage [ Select
] ["EX", "WB", "ID",
"MEM"] will the match occur, what buses will contain the
matching values [ Select
] ["I/IRegRS2-Rd", "RS2-M/WRegisterRd",
"RS1-E/MRegWr", "RS2-M/WRegWr", "RS2-E/MRegWr", "RS1-M/WRegWr",
"RS1-E/MRegisterRd", "RS2-E/MRegisterRd", "RS1-M/WRegisterRd",
"I/IRegRS1-Rd"] , what action
[ Select ]
["exception/interrupt", "stall/bubble",
"bypass/forward"] will occur as a result, what will be
the qualifying term [ Select
] ["E/M RegWr", "M/W RegWr",
"ID/EX.MemRead"] and what related data selector (mux)
input [ Select ]
["B", "0", "A", "F", "C", "D",
"E"] will be selected? What control signals, if any,
will be deasserted? [ Select
] ["PCWrite only", "IF/DWrite only",
"none", "PCWrite and IF/DWrite"]
What binary comparison will match next
[ Select ] ["01011", "00100",
"00101", "01001"] , in which pipeline stage
[ Select ]
["ID", "WB", "EX", "MEM"] , what busses will
contain the matching values [
Select ] ["RS2-E/MRegisterRd",
"RS1-E/MRegisterRd", "I/IRegRS1-Rd", "I/IRegRS2-Rd",
"RS2-M/WRegisterRd", "RS1-M/WRegisterRd"] , what
action [ Select ]
["exception/interrupt", "bypass/forward",
"stall/bubble"] will result, what will be the qualifying
term [ Select ]
["M/W RegWr", "ID/EX.MemRead", "E/M
RegWr"] and what related data selector (mux)
input [ Select ]
["E", "F", "0", "A", "D", "C",
"B"] will be selected? What control signals, if any,
will be deasserted? [ Select
] ["IF/DWrite only", "none", "PCWrite and
IF/DWrite", "PCWrite only"]
What binary comparison will match next
[ Select ] ["01011", "01001",
"00010", "00011"] , in which pipeline stage
[ Select ]
["MEM", "WB", "ID", "EX"] , what busses will
contain the matching values [
Select ] ["RS2-E/MRegisterRd",
"RS2-M/WRegisterRd", "RS1-M/WRegisterRd", "RS1-E/MRegisterRd",
"I/IRegRS1-Rd", "I/IRegRS2-Rd"] , what
action [ Select ]
["stall/bubble", "bypass/forward",
"exception/interrupt"] will result, what will be the
qualifying term [ Select
] ["E/M RegWr", "M/W RegWr",
"ID/EX.MemRead"] and what related data selector (mux)
input [ Select ]
["A", "E", "F", "0", "D", "C",
"B"] will be selected? What control signals, if any,
will be deasserted? [ Select
] ["IF/DWrite only", "none", "PCWrite and
IF/DWrite", "PCWrite only"]
What binary comparison will match next
[ Select ] ["01111", "00011",
"00100", "01001"] , in which pipeline stage
[ Select ]
["MEM", "ID", "WB", "EX"] , what busses will
contain the matching values [
Select ] ["RS2-E/MRegisterRd",
"I/IRegRS1-Rd", "RS1-E/MRegisterRd", "RS1-M/WRegisterRd",
"I/IRegRS2-Rd", "RS2-M/WRegisterRd"] , what
action [ Select ]
["stall/bubble", "exception/interrupt",
"bypass/forward"] will result, what will be the
qualifying term [ Select
] ["E/M RegWr", "ID/EX.MemRead", "M/W
RegWr"] and what related data selector (mux)
input [ Select ]
["A", "E", "0", "F", "B", "D",
"C"] will be selected? What control signals, if any,
will be deasserted? [ Select
] ["none", "PCWrite only", "PCWrite and
IF/DWrite", "IF/DWrite only"]
Hazard detection unit ID/EX. MemRead 1/ReRST I/Regs2 IF/DWrite ID/EX WB EX/MEM WB E/MRegWr M u Control! M M MEM/WB PC Write IF/ID 0 - EX M WB we A B M u с W Instruction Registers M we PC Instruction memory Forward > ALUI D D M E u FX Data memory ForwardB Immediate IF/ID. RegisterRs1 IF/ID. RegisterRs2 IF/ID. RegisterRd Rd E/M.RegisterRd Rs1 Rs2 Forwarding unit M/W.RegisterRd MIWRegWr For the code snippet below, refer to the schematic above if necessary to answer the following so as to achieve correct pipeline operation: lw x15, 0(x3) sub x4, x5, x4 lw x9, 0x3(x15) lw x9, 0x4(x9) xor X9, x3, x9