Answer Happy

Use the following Verilog module to answer the questions below:
a. Draw the logic diagram for the circuit that represents this code. Use the proper flip-flop symbols. (1 point)
module pb1 (
input clk, x, output reg y1, y2 );
wire w = x | (~y1);
always @(posedge clk) y2 <= w;
always @(negedge clk) y1 <= y2;
endmodule
Problem 1 - 3 points Use the following Verilog module to answer the questions below: a. Draw the logic diagram for the circuit that represents this code. Use the proper flip-flop symbols. (I point) module pb1 input clk, x, output reg y1, y2); wire w = x1(-y1); always @[posedge clk) y2 <= w; always @(negedge clk) y1 <= y2; endmodule b. Draw the output waveforms for the specified inputs. Assume that input x changes value shortly after the rising edges of clk. Further assume that the values of yl and y2 are not known at the beginning of the timing diagram. (2 points) clk x Х yi 1 - - - - 1 - y2 1 - 1 ! - - - 1 1 1 1