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module pb1 input clk, x, output reg y1, y2); wire w = x1( -1); always @(posedge clk) y2 <= w; always @(negedge clk) y1 <

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module pb1 input clk, x, output reg y1, y2); wire w = x1( -1); always @(posedge clk) y2 <= w; always @(negedge clk) y1 <

Posted: Fri May 20, 2022 11:45 pm
by answerhappygod
Module Pb1 Input Clk X Output Reg Y1 Y2 Wire W X1 1 Always Posedge Clk Y2 W Always Negedge Clk Y1 1
Module Pb1 Input Clk X Output Reg Y1 Y2 Wire W X1 1 Always Posedge Clk Y2 W Always Negedge Clk Y1 1 (6.12 KiB) Viewed 14 times
Draw the logic diagram for the circuit that represents
this code. Use the proper flip-flop symbols.
PLEASE AND THANK YOU
module pb1 input clk, x, output reg y1, y2); wire w = x1( -1); always @(posedge clk) y2 <= w; always @(negedge clk) y1 <= y2; endmodule
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