08. Design For the S-R latch, assume each NAND gate has a delay of 1 nsec. The inputs to the S-R latch are applied as fo
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08. Design For the S-R latch, assume each NAND gate has a delay of 1 nsec. The inputs to the S-R latch are applied as follows. At every 1 nsec, the value at S is given by 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1. At every 1 nsec, the value at R is given by 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1. Find out the waveform at the outputs, Q, Q' as functions of time. 5° R Page 1 of 2 Q9. Now assume that the top NAND gate has a delay of 1 nsec, while the bottom NAND gate has a delay of 2 nsec. Rework the above problem.