Answer Happy

below: a. Draw the logic diagram for the circuit that
represents
this code. Use the proper flip-flop symbols.
module pb1 (
input clk, x,
output reg y1, y2 );
wire w = x | (~y1);
always @(posedge clk)
y2 <= w;
always @(negedge clk)
y1 <= y2;
endmodule
b. Draw the output waveforms for the specified inputs. Assume
that input x changes value
shortly after the rising edges of clk. Further assume that the
values of y1 and y2 are not
known at the beginning of the timing diagram.
clk x yl y2