Design a Mealy logic circuit that receives binary information on a clock synchronised serial line. The circuit should ex
Posted: Fri May 20, 2022 9:26 pm
Design a Mealy logic circuit that receives binary information on a clock synchronised serial line. The circuit should examine non-overlapping and overlapping strings of 3 successive bits received on the serial line. The circuit should set its output high if the sequence { 1,0,1 } occurs.