3. (1). [11 points ] Draw the synthesized schematic for the following Verilog codes. reg ql. 42. w; wire a, b, c, d, e,
Posted: Fri May 20, 2022 7:08 pm
- 3 1 11 Points Draw The Synthesized Schematic For The Following Verilog Codes Reg Ql 42 W Wire A B C D E 1 (18.39 KiB) Viewed 32 times
- 3 1 11 Points Draw The Synthesized Schematic For The Following Verilog Codes Reg Ql 42 W Wire A B C D E 2 (19.23 KiB) Viewed 32 times
- 3 1 11 Points Draw The Synthesized Schematic For The Following Verilog Codes Reg Ql 42 W Wire A B C D E 3 (9.97 KiB) Viewed 32 times
3. (1). [11 points ] Draw the synthesized schematic for the following Verilog codes. reg ql. 42. w; wire a, b, c, d, e, f, s, Your Schematic assign d= -a& bc; assign - - (d^e): always@(posedge clk) begin ql <-(421 d); 42 f. end always @(s or ql or 2) begin if(s) w=q1; else w=42: end Page 4
(2) [15 points ] The ASM chart is given below. reset SO $2/y si X Complete the simulation waveform below based on the given ASM chart. The STATE signal represents the current state used in the finite state machine. The reset signal is asynchronous and high active.
CLK reset X 1 STATE Y W