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An SRAM has 8-bit databus and 6-bit address bus. The SRAM function table is shown below: WE CS OE VO Function Standby CS, WE, and OE signals in the above function table are high active. Design the above SRAM in VHDL X L х High- L H L High-z DOUT L H. H Output Disabled Read Data Wille Data H H х DIN library icee: use ieee.std_logic_1164.all: use ieee.std_logic_unsigned.all: entity ram is port address: data CS we i end ram; architecture beh_ram of ram is

use seee std logic 1164 all use ieee std_logic_unsigned all: entity ram 15 port address : data CS we ). oc end ram architecture beh ram of ram is I end beh ram