Answer Happy

Please see the above questions and answer them, and ignore the
answer that are written as I am not sure whether they are correct
or not.
1. [21 points__Mark the correct answer or fill out blanks for the following questions. Every question has only one correct answer. 1).[True ] I. 1). [V True] [_False] The diagram below shows parallel JTAG boundary scan. TMS TCK TMS TCK DEVICE 1 TMS TCK DEVICE 2 TDI TDO TMS TCK DEVICE 3 TDI TDO TDI TDI TDO TDOO INT i 2). [V True] [__ False] The BYPASS register in the JTAG boundary scan is used for internal test of the logic circuits inside the chip.

3). [_True) [ False_The circuit below has static-0 hazard. A B ♡ D 4). [_True) [VFalse] Reducing the data rate can increase the mean time between failure (MTBF) value. 5). [True] [_ False] Xilinx CLB is used to implement the input and output functions of an FPGA device.

6). Which diagram below shows the correct figure for the Verilog code below? and #(2, 1) (F, A, B): A A 1 A B B + HE 1 1 B 1 F 1 01 1 F LL 01 F1 LI 0 1 1 3 1 5 1 8 9 3 4 1 3 89 1 5 12 time 12 time 12 time 8 9 10 Figure 1. Figure 2. Figure 3. The correct figure is figure 1 Page 2

7). The transmission line circuit is shown below. SIC Z = 4002 Vsrc = 5V Zoad = 30022 Ζ = 100Ω Calculate reflection coefficient at the load pload. Your answer Calculate the load voltage after the first reflection. Your answer: Calculate the steady state load voltage. Your answer 0.5 0.5 : 2.14