Answer Happy

For next 5 questions, consider and a sequence of twelve
memory references as 8-bit word addresses (hexadecimal
numbers):
0x05, 0x06, 0x08, 0x07, 0x15, 0x0F, 0x0C, 0x05, 0x09, 0x08,
0x0E, 0x07
and a cache of total size 16 words.
a.)
If the cache is organized as directed mapped with 1-word blocks
and initially empty, what is the number of cache misses for the
given sequence of memory references?
Select one:
A.
8
B.
9
C.
10
D.
11
E.
None of the above
b.)
If the 16-word cache is organized as 2-way set associative with
2-word blocks and initially empty (assuming LRU replacement
strategy), how many bits in the word address are for the "block
offset", "cache index" and "tag" fields, respectively?
Select one:
A.
0, 4, 4
B.
1, 2, 5
C.
2, 1, 5
D.
2, 0, 6
E.
0, 2, 6
c.)
If the cache is organized as 2-way set associative with 2-word
blocks and initially empty (assuming LRU replacement strategy),
what is the number of cache misses for the given sequence of memory
references?
Select one:
A.
5
B.
6
C.
7
D.
8
E.
9
d.)
If the 16-word cache is organized as fully associative with
4-word blocks and initially empty (assuming LRU replacement
strategy), how many bits in the word address are for the "block
offset", "cache index" and "tag" fields, respectively?
Select one:
A.
0, 2, 6
B.
1, 1, 6
C.
2, 1, 5
D.
2, 0, 6
E.
1, 2, 5
e.)
If the cache is organized as fully associative with 4-word
blocks and initially empty (assuming LRU replacement strategy),
what is the number of cache misses for the given sequence of memory
references?
Select one:
A.
4
B.
5
C.
6
D.
7
E.
8