Answer Happy

a.)Which of the following statements is true about the 5-staged
pipelined processor.
Select one:
A.
Pipelined processor doesn't reduce instruction latency, but
increases instruction throughput over the single-cycle
processor.
B.
Pipelined processor reduces instruction latency by a factor of 5
over single-cycle processor (minus some overheads), and increases
instruction throughput.
C.
Pipelined processor reduces instruction latency by a factor of 5
over single-cycle processor (minus some overheads), and reduces
instruction throughput.
D.
Pipelined processor doesn't affect instruction throughput, but
reduces instruction latency over the single-cycle processor.
E.
None of the above.
b)
Consider the 5-stage pipelined processor for the MIPS ISA.
Assuming the following latencies for the major functional units in
processor design and ignoring the delays of multiplexers and
wires.
Instr-Mem
Register read
ALU or Adder
Data-Mem
Register write
Latency
1.5 ns
0.5 ns
1 ns
1.5 ns
0.5 ns
What is the shortest cycle time for this pipelined
processor?
c.)
Ignoring pipeline stalls, what is the speedup of the ideal
5-stage pipelined processor compared to the single-cycle processor
using those functional units?
d)
Assume a 5-stage MIPS pipeline processor has a branch
predictor with accuracy of 80% and determines branch outcome in the
ID stage (i.e. one instruction is flushed if the prediction is
wrong). Consider a program with 20% of its instructions as branch
instructions, and assume an ideal CPI of 1 for non-branch
instructions. What is the overall CPI of this
program?