In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time
Posted: Fri May 20, 2022 12:34 pm
In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory miss penalty takes 70 ns and that memory accesses are 36% of all instructions. The following table shows data for Li caches attached to each of two processors, P1 and P2. Ll Size LI Miss Rate Ll Hit Time P1 2 KB 7.0% 0.70 ns P2 4 KB 6.0% 0.90 ns Assuming that the u hit time determines the cycle times for P1 and P2, what are their respective clock rates? a. What is the Average Memory Access Time for P1 and P2? b. Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?