Question 1: Design the basic ECL (IQ, IC and VR) logic gate in Figure 1 such that the maximum power dissipation is 0.2 m
Posted: Sun May 15, 2022 9:19 pm
Question 1:
Design the basic ECL (IQ, IC and VR) logic gate in Figure 1 such
that the maximum power dissipation is 0.2 mW and the logic swing is
0.4 V. [10 Marks]
[Hint: Logic swing is the voltage difference between logic
HIGH and LOW]
Use activation voltage 𝑽𝜸(𝒅𝒊𝒐𝒅𝒆)= 0.6V, 𝑽𝜸(𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓)=
0.5V, 𝑽𝑩𝑬 (𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝒂𝒄𝒕𝒊𝒗𝒆)=𝟎.𝟕𝑽, 𝑽𝑫=𝟎.𝟕𝑽 𝑎𝑛𝑑 𝑽𝑩𝑬(𝒔𝒂𝒕)=𝟎.𝟖 𝑽 for all
the questions.
Vcc=1.7 V 'Rc -ovo VO UX *** ya Q2 OR OVR
Design the basic ECL (IQ, IC and VR) logic gate in Figure 1 such
that the maximum power dissipation is 0.2 mW and the logic swing is
0.4 V. [10 Marks]
[Hint: Logic swing is the voltage difference between logic
HIGH and LOW]
- Question 1 Design The Basic Ecl Iq Ic And Vr Logic Gate In Figure 1 Such That The Maximum Power Dissipation Is 0 2 M 1 (30.22 KiB) Viewed 29 times
0.5V, 𝑽𝑩𝑬 (𝒇𝒐𝒓𝒘𝒂𝒓𝒅 𝒂𝒄𝒕𝒊𝒗𝒆)=𝟎.𝟕𝑽, 𝑽𝑫=𝟎.𝟕𝑽 𝑎𝑛𝑑 𝑽𝑩𝑬(𝒔𝒂𝒕)=𝟎.𝟖 𝑽 for all
the questions.
Vcc=1.7 V 'Rc -ovo VO UX *** ya Q2 OR OVR