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Division by Constant As you know division operator cannot be synthesized in a general case and it is dependent on the synthesis tool. In this assignment we consider a special case of division operation which is division by constant. Consider an unsigned integer division by constant circuit that accepts an input of 8 bit wide and divides it by constant value 47. This divider circuit accepts an 8-bit input and generates two output values: remainder and quotient. As an example, if input is 109, the remainder is 15 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. The entity is given below for your reference: entitiy DIV_CONST is port (dividend: in std_logic_vector(7 downto 0); remainder: out: std_logic_vector(5 downto 0); quotient: out std_logic_vector(2 downto 0)); end DIV_CONST; Design a synthesizable integer division by 57 circuit Design your circuit for minimum area. Hint: Use the repeated subtraction method to synthesize this circuit. Do not use any loop. 1. Explain how the number of bits in entity declaration are chosen (5 points) 2. Draw a block diagram of the complete design that implements your algorithm (15 points) 3. Write a VHDL code to model this division by constant circuit using concurrent conditional statements. (25 points) 4. Write a VHDL code to model this division by constant circuit using sequential conditional statements (25 points) 5. Find out if this division by constant is synthesizable by Vivado tools or not. You need to write a simple statement and divide the input by constant 47 using VHDL division operator. Does your design compile? If yes, what is the difference between the circuit you designed and the circuit synthesized by the Vivado tools? (10 points) 6. Write VHDL testbenches to verify your designs. Present a test vector that verifies the design functionality for all cases. (20 points) GOOD LUCK!