Answer Happy

Draw the state diagram for the VHDL code
below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TrafficLight is
generic(clk_freq : integer);
port(
Clk : in std_logic;
nReset : in std_logic; --
Negative reset
North_South_Red : out std_logic;
North_South_Yellow : out std_logic;
North_South_Green : out std_logic;
East_West_red : out std_logic;
East_West_Yellow : out std_logic;
East_West_Green : out std_logic);
end entity;

architecture rtl of TrafficLight is

type State_type is (North_Next, Start_North_South,
North, Stop_North_South, East_West_Next, StartWest, East_West,
Stop_East_West);
signal State : State_type;
signal Time_Counter : integer range 0 to clk_freq *
60; --used for counting clock Periods

begin

process(Clk) is
begin
if rising_edge(Clk) then

if nReset = '0' then
State
<= North_Next;

Time_Counter <= 0;

North_South_Red <= '1';

North_South_Yellow <= '0';

North_South_Green <= '0';

East_West_red <= '1';

East_West_Yellow <= '0';

East_West_Green <= '0';

else
-- Default
values

North_South_Red <= '0';

North_South_Yellow <= '0';

North_South_Green <= '0';

East_West_red <= '0';

East_West_Yellow <= '0';

East_West_Green <= '0';


Time_Counter <= Time_Counter + 1;

case State
is


when North_Next =>

North_South_Red <= '1';

East_West_red <= '1';
if Time_Counter = clk_freq * 5 -1 then
-- 5 second passed

Time_Counter <= 0;

State <=
Start_North_South;

end if;


when Start_North_South =>

North_South_Red <= '1';

North_South_Yellow <= '1';

East_West_red <= '1';
if Time_Counter = clk_freq * 5 -1 then

Time_Counter <= 0;

State <= North;

end if;


when North =>

North_South_Green <= '1';

East_West_red <= '1';
if Time_Counter = clk_freq * 60 -1 then
-- 1 min passed

Time_Counter <= 0;

State <=
Stop_North_South;

end if;


when Stop_North_South =>

North_South_Yellow <= '1';

East_West_red <= '1';
if Time_Counter = clk_freq * 5 -1 then -
5 seconds passed

Time_Counter <= 0;

State <=
East_West_Next;

end if;


when East_West_Next =>

North_South_Red <= '1';

East_West_red <= '1';
if Time_Counter = clk_freq * 5 -1 then

Time_Counter <= 0;

State <=
StartWest;

end if;


when StartWest =>

North_South_Red <= '1';

East_West_red <= '1';

East_West_Yellow <= '1';
if Time_Counter = clk_freq * 5 -1 then

Time_Counter <= 0;

State <=
East_West;

end if;


when East_West =>

North_South_Red <= '1';

East_West_Green <= '1';
if Time_Counter = clk_freq * 60 -1 then

Time_Counter <= 0;

State <=
Stop_East_West;

end if;


when Stop_East_West =>

North_South_Red <= '1';

East_West_Yellow <= '1';
if Time_Counter = clk_freq * 5 -1 then

Time_Counter <= 0;

State <=
North_Next;

end if;

end
case;

end if;
end if;
end process;

end architecture;