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Consider a fictitious and very simple Von-Neumann architecture with 8-bit addresses, 4 12-bit registers, and 4 instructi
Posted: Sun May 15, 2022 6:56 pm
by answerhappygod
- Consider A Fictitious And Very Simple Von Neumann Architecture With 8 Bit Addresses 4 12 Bit Registers And 4 Instructi 1 (309.09 KiB) Viewed 51 times
Consider a fictitious and very simple Von-Neumann architecture with 8-bit addresses, 4 12-bit registers, and 4 instructions: LOAD, STORE, ADD and STOP. Each instruction is encoded with 12 bits: the first 2 bits give the opcode (to identify the instruction), the next 2 bits give the number of the register that the instruction operates with, and the last 8 bits are an operand (that is interpreted as either an address or an 8-bit positive integer number, depending on the instruction). This architecture is depicted in the figure below. Hint: what is the initial value of PC? Address (8 bits) Value (12 bits) 0000 0000 0000 program counter 00000001 current instruction register register 0000 0000 0000 0000 0000 0111 0000 0000 0000 register 0000 0000 0000 0001 0000 0010 0000 0011 00001 0000 0101 0000 0110 0010 1011 1111 0000 1111 ON 1011 0000 0100 0110 11111 0111 DOLL MILLON 1011 0000 1101010 0101 ALU Control Unit 1111 0000 CPU 1111 0010 1111 0011 1111 0100 TIL 0101 11110110 111111 TIIT 1000 1111 1001 0101111111111 1100 1010 1101 0000 0000 0000 0000 0000 0111 000111111011 0000 0000 1111 0000 0000 0000 000001000001 0000 0000 111111 0000 0000 0000 RAM 8-bit 2-bit 2-bit opcode register ID operand 12-bit instruction Instruction opcode 00 LOAD STORE 01 description Load the value at the address (operand) into the register (ID) Store the value in the register (ID) at the address (operand) Add to the register (ID) the operand (interpreted as a positive integer) Finish execution (ID and operand are ignored) ADD 10 STOP 11