thank you :)
Posted: Sun May 15, 2022 6:32 pm
thank you 
BACKGROUND INFO: IN THE FIRST PICTURE BELOW IS A 4X6 ROM SCHEMATIC WITH TWO ADDRESS BITS, 4 ROWS AND 6 COLUMNS (SECOND PICTURE), THE VALUES STORED IN THE ROM, AND THE DOT REPRESENTATION OF THOSE BITS THAT CORRESPOND TO THE ROM CONTENTS. THE ROM IMPLEMENTS O LOGIC FUNCTIONS (YO-Y5) OF TWO VARIABLES EACH (AO-Al). THE 2:4 ADDRESS DECODER IMPLEMENTS THE FIXED "AND" PLANE OF ALL TERMS (SUCH AS m0=al'a0', ml=al'a, m2=ala0', m3=alaO) AND THE ARRAY IMPLEMENTS SIX LOGIC FUNCTIONS Y5=m3m2, Y4=mlmo, Y3=m3ml, Y2=m2mo, Yl=m3, YO=m2mlmo QUESTION: A: IMPLEMENT FUNCTIONS Y3 AND YO. SKETCH THE DOT REPRESENTATION FOR A CIRCUIT WITH INPUTS Al-A0 AND OUTPUTS Y3-YO 2 B: WITH TWO FUNCTIONS Y3 AND YO, SKETCH THE DOT REPRESENTATION FOR THE CIRCUIT WITH INPUTS Al-AO AND OUTPUTS Y3-YO.
Α1 ΑΟ weak pseudo-nMOS pullups 2.4 DEC 1 CHE ICH [ HC ROM Array d Y5 Y4 Y3 Y2 71 YO
Word 0: 010101 Word 1: 011001 Word 2 : 100101 Word 3: 101010
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Α1 ΑΟ weak pseudo-nMOS pullups 2.4 DEC 1 CHE ICH [ HC ROM Array d Y5 Y4 Y3 Y2 71 YO
Word 0: 010101 Word 1: 011001 Word 2 : 100101 Word 3: 101010