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Q7. A circuit composed of edge-trigger DFFs which are all initially RESET is shown in the figure 4-7(a). Complete the timing diagram of this circuit in figure 4-7(b) by showing the output waveform of Q1, Q2, Y and Z. A cpnnnn D D 2 A CP Fig. 4-7(a) Fig. 4-7(b)

Q1. The RS latch consists of NOR gate is shown in figure 4-1(a). Write the state transition truth table and the state equation of the circuit. If the waveform of S, and R, is shown in figure 4-1(b), please determine the output waveform of Q and © . Sot So Q R R, > R, Fig. 4-1(a) Fig. 4-1(b)