For the code provided below identify the sequence of outputs in hexadecimal to complete the sequence table below. The ou
Posted: Sun May 15, 2022 4:06 pm
For the code provided below identify the sequence of outputs in hexadecimal to complete the sequence table below. The output corresponds to present state.
hexadecimal to complete the sequence lable below. The output corresponds to the present stale.: Clock Period Present State SW Ned State 30000(80) 2000 30001 (S1) 2 30001(SI), 2'b11 36100 (SA) 3 3b 100 2600 3072 4 3 ?? 2b10 3D? S SUI?? 2b10 3D? 6 30??? 2010 3072? 7 30??? 2010 30??? 8 3 ?? 2011 3072? LED in Hex 8H44 8H84 SH (0) 8H 8H SHO SHO HO Verilog Code: • module Tight24 output reg [7:9 LED, U LED array, has to be register type. input[1:07 SW, 12 bit vector for the four possible inputs combinations • input dk ll clock signal • reg (20) state, next stale; : Define alias for state values 3 parameter SO=3000, SI-30001, o S2-30010, • S-30011. • S-30100, - SS-30101, 56-3b110, Not used but defined as an example • 57-3b111; not used but defined as an example 트 - Change to next stat only on transition of clock, always (posedge dk) • slate next stale, Il Future state becomes the present stale . • Define ned state
• Define next state : always Q[state or Swo State changes • case(state) so: case (SW) Forslale validate al cases of SW 2 switches 2000: next_stale-St; 2001: next_stale-St; • 2010: nexd_state-St; 2b1t: neid state-St; endcase • St: case (SW) For state validate al cases of SW 2 switches 2000: next_stale=S2 200t: next stale-St; 2010: next_stalesz • 2dit: nest_stale-St; endcase S2 case (SW)! For state validate al cases of SW 2 switches 2000: nexd_stale-S3, • 2001: next_stale S3, • 2010: next_state-53; • 2b1t: neat_state-S3, • endcase • S3: case (SW) For state validate al cases of SW 2 switches • 2000: ned_stales 2001: next_state-S0; • 2010: next_stale SS, • 2b1t: next_state-SS, • endcase . Se case (SW). For state validate al cases of SW 2 switches • 2000: next state-52 • 200t: nest staleS2 • 2010: ned_state-S2 • 2011: ned_state-S2, . endcase • SS: case (SW) For state validate al cases of SW 2 switches • 2000: next_state=SO, • 2001: ned_state=SO, • 2010. ned_state=S0, • 2b11: ned_state-SO; endcase . default ned_state-50, • endcase always @(state) Moore outputs
. always @(state) // Moore outputs • case(state) • SO: LED S'H44; • S1: LED S'H84; • S2: LED S'H25; • S3: LED 8'H26; • S4: LED S'H30; • SS: LED S'H86; • S6: LED 8H28; • S7: LED 8'H87; • INED 7 indicates an undefined state output and the last 3 bits are the state value • default begin LED[2:0]<=state; LED[7:3]<=5b10000; end endcase • endmodule [a] IC くくくくくく A. 44 B. 26 C. 86 D.30 E. 25 F. 84 [d [e]
- For The Code Provided Below Identify The Sequence Of Outputs In Hexadecimal To Complete The Sequence Table Below The Ou 1 (148.9 KiB) Viewed 64 times
- For The Code Provided Below Identify The Sequence Of Outputs In Hexadecimal To Complete The Sequence Table Below The Ou 2 (121.79 KiB) Viewed 64 times
- For The Code Provided Below Identify The Sequence Of Outputs In Hexadecimal To Complete The Sequence Table Below The Ou 3 (114.72 KiB) Viewed 64 times
• Define next state : always Q[state or Swo State changes • case(state) so: case (SW) Forslale validate al cases of SW 2 switches 2000: next_stale-St; 2001: next_stale-St; • 2010: nexd_state-St; 2b1t: neid state-St; endcase • St: case (SW) For state validate al cases of SW 2 switches 2000: next_stale=S2 200t: next stale-St; 2010: next_stalesz • 2dit: nest_stale-St; endcase S2 case (SW)! For state validate al cases of SW 2 switches 2000: nexd_stale-S3, • 2001: next_stale S3, • 2010: next_state-53; • 2b1t: neat_state-S3, • endcase • S3: case (SW) For state validate al cases of SW 2 switches • 2000: ned_stales 2001: next_state-S0; • 2010: next_stale SS, • 2b1t: next_state-SS, • endcase . Se case (SW). For state validate al cases of SW 2 switches • 2000: next state-52 • 200t: nest staleS2 • 2010: ned_state-S2 • 2011: ned_state-S2, . endcase • SS: case (SW) For state validate al cases of SW 2 switches • 2000: next_state=SO, • 2001: ned_state=SO, • 2010. ned_state=S0, • 2b11: ned_state-SO; endcase . default ned_state-50, • endcase always @(state) Moore outputs
. always @(state) // Moore outputs • case(state) • SO: LED S'H44; • S1: LED S'H84; • S2: LED S'H25; • S3: LED 8'H26; • S4: LED S'H30; • SS: LED S'H86; • S6: LED 8H28; • S7: LED 8'H87; • INED 7 indicates an undefined state output and the last 3 bits are the state value • default begin LED[2:0]<=state; LED[7:3]<=5b10000; end endcase • endmodule [a] IC くくくくくく A. 44 B. 26 C. 86 D.30 E. 25 F. 84 [d [e]