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Page 2 > of 2 ZOOM + 7. Exercise in Pairs: Work with a partner to solve this question (which is based on Practice Question 274). The circuit below generates an enable signal, regen, that fans out to 64 registers. Its propagation delay is too slow. 5 9999 1 1 DQhQD Q1 en en en regen 40 at en 1x a) Estimate the delay of the circuit using the linear delay model and the table of values below to calculate the propagation delay along a path from one of the inputs to regen. Assume that each of the 64 flip-flops connected to regen presents 9Cof load capacitance. Gate NOT n-input NAND n-input NOR n-input Inverting MUX XOR2 or XNOR2 Logical Parasitic 1x Gate Cffort (g) ( Delay (P) (o Input Capacitance 1 1 1 30g (n+2)/3 n (n+2) (2n+1)/3 n (2n+1) 2 2n 6C, 4 4 120 b) Which terms in the previous question contribute most to the propagation delay? c) Write a list of strategies that could possibly speed up the circuit. Sketch a circuit for each. Remember there is more than one logic circuit that could be used to generate the regen signal. You may like to consider the following hints: • How might you use a gate with low logical effort to drive the large capacitive load? • The 5 input NAND gate has large logical effort and parasitic delay. How might you rearrange the circuit to avoid a gate with such large fan-in? There is more than one way to do this! • What do the 'lx' symbols mean on the diagram? How might this help you speed up the circuit? more d) Choosing the best circuit to minimise delay is not straight-forward. Pick a modified circuit based on one or the strategies you identified above and find its propagation delay. 8. Reflection Tenishi butube Wht blu kutube and their orter