•Design a 4-bit Parallel In Serial Out (PISO) shift register. •It has one 1-bit output: Q. •It has four inputs: CLK, RES
Posted: Sun May 15, 2022 12:30 pm
•Design a 4-bit Parallel In Serial Out (PISO) shift
register.
•It has one 1-bit output: Q.
•It has four inputs: CLK, RESET, D[3:0], and L.
–CLK is the clock.
–When RESET=1, the output should become 0.
–If L=1, D is stored to the shift register.
–The output Q is the most significant bit of the shift
register.
–If L=0, the bits in the shift register shift to the upper
place. The least significant bit is padded with 0.
•Examples are given at the following image
Example L L D Q Register 1011 1 1011 OP 10 1 0 0110 0 1100 1 0 1000 1 1 0101 0101 0 0 1010 1 1 0010 0010 0 O O 0 0100 0
register.
•It has one 1-bit output: Q.
•It has four inputs: CLK, RESET, D[3:0], and L.
–CLK is the clock.
–When RESET=1, the output should become 0.
–If L=1, D is stored to the shift register.
–The output Q is the most significant bit of the shift
register.
–If L=0, the bits in the shift register shift to the upper
place. The least significant bit is padded with 0.
•Examples are given at the following image
- Design A 4 Bit Parallel In Serial Out Piso Shift Register It Has One 1 Bit Output Q It Has Four Inputs Clk Res 1 (201.06 KiB) Viewed 96 times