Problem 3. (20pt) Timing analysis Consider the following circuit and delay parameters. D PI Parameter ipca tsetup tpd_no
Posted: Sun May 15, 2022 12:12 pm
Problem 3. (20pt) Timing analysis Consider the following circuit and delay parameters. D PI Parameter ipca tsetup tpd_not Value Meaning 5 ps Propagation delay of a D flip-flop 5 ps Setup time 10 ps Propagation delay of a NOT gate 25 ps Propagation delay of an AND gate 25 ps Propagation delay of an OR gate 30 ps Propagation delay of a XOR & gate tpd_and tpd_or tpd_xor (a) If there is no clock skew, what is the maximum operating clock frequency of the circuit? (b) How much clock skew can the circuit tolerate if it must operate at 8 GHz (the hold time violation is not considered)?