Answer Happy

5. [15 pts] State machine diagram These two figures show a finite-state transition diagram for a single private cache blocking using a write invalidation protocol and a write-back cache. First figure shows the cache state transitions based on requests from CPU and the second figure shows cache state transitions based on requests from the bus. Please explain what context would cause the state transition and what bus actions would be generated or transactions would be placed on bus for 12345 1 Place write, miss on bus 2 CPU write miss, place write miss on bus 3 CPU read miss write-back block, place read miss on bus 4 Write-back block; abort memory access 5 Write-back block; abort memory access

Figurel: CPU Read hit CPU read Invalid Place read miss on bus Shared (read only) CPU read miss Place read miss on bus CPU Write (1 Place invalidate on bus Exclusive (read/ write) CPU Write hit CPU Read hit CPU Write Miss Write-back cache block Place write miss on bus Figure2: Write miss for this block Invalidate for this block Invalid Shared (read only) CPU read miss Exclusive (read/ write)