Answer Happy

MIR A bus Bbus C bus 0 PC 1 AC ANUN A N 2 N SP 3 TIR The microstruction layout for min de der 5 6 -1 AMASK 9 SMASK 10 11 12 13 14 15 A latch Blatch Address out MAR To address bus To data bus : My Data in MOR M "M AAMUX Fo F:- ALU Shifter Data out

VERTICAL M CROARCH TECTURE AND R1 decoder R? decoder Clock Subcycles 18 registers Mux AstchBlatch Increment MPC MAR MBR 256 x 12 Control store Micro Amux loglo MIR OP R1 R2 ALU OP Decode Shitter RD WR Fig. 4-18. A microarchitecture with vertical microinstructions. Example of OP Assignment for Vertical Architecture OP estruction Register Assignment OF Instruction Register Assignment 0 VAR EZ GOTOX 1 XEMER 9 X=XY RieX, RY RD NA 10 XANDEX,Y: RieX, RY 3 NA 11 x RieX, RZY MER 12 XENOT VS ReX, R2-Y 3 XSTV RieX, RZY 34 XSTV ReX, RY 6 GOTOX 33 MARX ReX, RY 7 EN GOTOX MERY: WR WE 4

D Use the microarchitecture handout and show the decimal value representation for each field of microcode of the following instructions. Identify do not care by using an asterisk (***). Use the table below to complete your answer. in your answer, separate each cell by ". AMUX COND ALUSH MBR MARRD WRENC CBA ADDR

IR: - MBR; GOTO 68; ;