Spring 20 8(a) (5 pts) Below Verilog code provides memory reading/writing operations. Both reading and writing are synch

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Spring 20 8 A 5 Pts Below Verilog Code Provides Memory Reading Writing Operations Both Reading And Writing Are Synch 1 (56.78 KiB) Viewed 81 times

Spring 20 8(a) (5 pts) Below Verilog code provides memory reading/writing operations. Both reading and writing are synchronous to clock signals. Change the code to provide an asynchronous reading. module Memory (Address, CLK, MemWrite, Data_In, Data_Out); output [31:0) Data_Out; input (6:0) Address; input CLK; input MemWrite; input [31:0] Data_In; reg [31:0) Data_Out; reg [31:0) DataMEM [0:127]; always @ (posedge CLK) begin if (MemWrite == 1'51) DataMEM[Address] <= Data_In; // writing else Data_Out = DataMEM[Address]; // reading end endmodule (b) (5 pts) Estimate how many AND gates and adders are required to design a 3 bits x 3 bits array multiplier? [Assume that only full adders are available] [**You don't need to draw an array multiplier)