6 (a) (6 pts) Complete the below Verilog function which will return a binary number (the input (4-bit binary number) x 8
Posted: Sat May 14, 2022 8:06 pm
6 (a) (6 pts) Complete the below Verilog function which will return a binary number (the input (4-bit binary number) x 8). The function name should be "left shift_by_3". function endfunction (b) (4 pts) Consider a 4-bit carry lookahead (CLA) structure. If two numbers A and B are given below, (i) what is the value of P3.0 (one of the outputs of CLA block) where P stands for propagation? Also, ii) what is the gate delay from the input A and B to get P3.0? [Restrictions: AOI (And, Or, Inverter) design with the limitation of 4-input. Assume the same gate delay for And, Or, and Inverter.] А B А А B Partial Full Adder Partial Full Adder Partial Full Adder GP Partial Full Adder 5 GP 5 GP с s C 5 GP C S 5 G 다. GP, Carry Look-Ahead Logic 6200 Prot A=1110, B-0001