simulate in ModelSim and synthesize in SynplifyPro
Posted: Sat May 14, 2022 3:42 pm
- Simulate In Modelsim And Synthesize In Synplifypro 1 (30.17 KiB) Viewed 47 times
SystemVerilog module sillyfunction(input logic a, b, c, output logic y); assign y=~a &~b &~C | a &~b &~C1 b ~ a & ~b & C; endmodule