Answer Happy

4. Consider the following assembly language code:
I0: add$t1,$s0,$t4
I1: add$t1,$t1,$t5
I2: lw$s0, value
I3: add$s1,$s0,$s1
I4: add$t1,$t1,$s0
I5: lw$t7,($s0)
I6: bnez$t7, loop
I7: add$t1,$t1,$s0
4. Consider the following assembly language code: 10: add $t1,$30, $t4 11: add $t1,$t1,$t 5 I2: lw $30, value I3: add $31, $30, $31 14: add $1$t1,$ = 0 15: lw $t7, ($30) 16: bez $t7, loop 17: add $t1,$t1,$30 Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of forwarding/bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). What is the final execution time of the code? TO T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 add $t1,$30, $t4 IF ID EX MEM WB add $t1,$t1,$t 5 IF ID EX MEM WB lw $30, value IF ID EX MEM WB add $31, $30, $31 $, IF ID EX MEM WB add #t,#ti, 30 IF ID EX MEM WB lw $57, (630) IF ID EX MEM WB lonez $t7, loop IF ID EX MEM WB add $t1,$t1,$30 =, IF ID EX MEM WB Total Cycles used: