Answer Happy

Part 1: ASM HAWK Create a complete state transition table for
the given ASM HAWK system (Pre-lab #8 document) Part 2: RTL
addition to ASM HAWK design Complete the RTL Design Tasks specified
in the Pre-lab #8 document (adding a countdown to the HAWK) Lab
Procedure: Part 1 – (to be completed within the first session of
Lab 8) 1. In a new project in Xilinx Vivado, create a new design
source (name it: hawk_controller) and write the code for the HAWK
using the given ASM chart and the state table crated in Part 1 of
the Design Task. You controller should have state transition, next
state logic, and output logic just like any other finite state
machine. Your controller module should have ‘clock’, ‘YP’ and ‘NS’
as inputs and the lights (HYL, HRL, HDNW, HW), present state, and
next state as outputs. 2. Simulate your design using a Verilog
Testbench. • The initial values of all your inputs should be 0. •
After a delay of 120 ns, set ‘YP’ to 1 for 50 ns to simulate a
person pressing the button. • Then, after a delay of 200 ns, set
‘NS’ to 1 to indicate that the person has finished crossing the
road. You can stop the simulation 200 ns after this point. • The
clock period should be set to 10 ns. 3. Check if the simulation
output is consistent with the design requirements. 4. Create a
constraints file in your project and set your I/O as follows: a)
Set your traffic lights (HYL, HRL, HDNW, HW) to be displayed from
on LED[3] to LED[0] in the given order. Set your present state to
be displayed on LED[15] to LED[12] in order. University of Texas at
El Paso EE 2169 –Laboratory for Digital Systems Design I - EE b)
Use SW[0] for your ‘YP’ input, and SW[1] for your ‘NS’ input. c)
Use the middle push button (btnC) as your clock input. 5. You will
need to include the following line in your constraints file to
disable the internal clock of the FPGA. Here, ‘clock1’ is the name
of the clock input in your module. Change it as needed. 6.
Synthesize and implement your module, and then generate the
Bitstream file. 7. Program the target device (Basys-3 FPGA) with
the Bitstream file generated in previous step. 8. Initially, use
the switches to set both ‘YP’ and ‘NS’ to zero and pulse the clock
using the push button and observe the LEDs. Then, set ‘YP’ to 1 and
note what happens when the clock is pulsed 10-12 times. Now set
‘NS’ to 1 and observe the effect of further pulsing the clock. Part
2 – (to be completed within the second session of Lab 8) 1. In the
same project from Part 1, create a new design source (name it:
hawk_datapath) and write the code for the counter from the Part 2
of the design task. Your counter module should have ‘clock’,
“set_count” and “act_count” as inputs, and the 4-bit count value as
output. 2. Modify the hawk_controller that you created for part 1
to include “set_count” and “act_count” as outputs that will be used
to control the datapath unit and “C” as a new input which will be
coming from the datapath unit. “C” is the present count value. Use
Figure 5 in the Pre-lab #8 doc-ument as reference and include the
following functionality in the controller. • Now, when your system
gets the ‘NS = 1’ signal in state 8, it will set “set_count” to 1
and go to a new state (you may use any of the unused states ‘D’,
‘E’, ‘F’). • In this new state, the “act_count” output of the
controller should be set to 1 (this will cause the counter in
hawk_datapath to count down at each clock pulse), and the system
should stay in this state until the count reaches zero. • Once the
count reaches zero, the system should go to state 9 just like in
the previous design. 3. Create a new design source (name it:
hawk_main) and use it to connect the HAWK controller and the
datapath counter. The inputs for this main module should be
‘clock’, ‘YP’ and ‘NS’, and the outputs should be any variable you
want to observe (at least the lights and present state). The code
inside this module should simply be the following: 4. Simulate your
design using a Verilog Testbench. • The initial values of all your
inputs should be 0. • After a delay of 120 ns, set ‘YP’ to 1 for 50
ns to simulate a person pressing the button. • Then, after a delay
of 200 ns, set ‘NS’ to 1 to indicate that the person has finished
crossing the road. You can stop the simulation 400 ns after this
point. • The clock period should be set to 10 ns. 5. Check if the
simulation output is consistent with the design requirements. 6.
Create a constraints file in your project and set your I/O as
follows: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets
clock1_IBUF] hawk_controller C1(Your controller inputs and
outputs); hawk_datapath D1(Your datapath inputs and outputs);
University of Texas at El Paso EE 2169 –Laboratory for Digital
Systems Design I - EE b. Set your traffic lights (HYL, HRL, HDNW,
HW) to be displayed from on LED[3] to LED[0] in the given order.
Set your present state to be displayed on LED[15] to LED[12] in
order. c. Use SW[0] for your ‘YP’ input, and SW[1] for your ‘NS’
input. d. Use the middle push button (btnC) as your clock input. 7.
You will need to include the following line in your constraints
file to disable the internal clock of the FPGA. Here, ‘clock1’ is
the name of the clock input in your module. Change it as needed. 8.
Synthesize and implement your module, and then generate the
Bitstream file. 9. Program the target device (Basys-3 FPGA) with
the Bitstream file generated in previous step. 10. Initially, use
the switches to set both ‘YP’ and ‘NS’ to zero and pulse the clock
using the push button and observe the LEDs. Then, set ‘YP’ to 1 and
note what happens when the clock is pulsed 10-12 times. Now set
‘NS’ to 1 and observe the effect of further pulsing the clock.
Demonstration and Documentation 1. The Demonstration part of this
lab is split over two lab sessions. In each session, you are
required to demonstrate the successful completion of the
corresponding procedure tasks to the TA. Suc-cessful completion for
each part is indicated by the outputs from the FPGA implementation
and testbench simulation both being consistent with the given
design task for that part. 2. Complete the Lab Report 8 assignment
on Gradescope within the specified deadline. This as-signment will
become available after the Prelab 8 due date. You will need to
include screen-shots of your Verilog module, Vivado timing diagram
outputs, constraints files as well as a pic-ture of the Basys-3
board running your designs within that assignment. set_property
CLOCK_DEDICATED_ROUTE FALSE [get_nets clock1_IBUF