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In this problem you will implement an FSM that counts 1s and ignores Os in the input x. The circuit outputs z = 1 if the number of 1s seen so far is a multiple of 3. In other words, z = 1 if the circuit has seen 3k ones and z= 0 if it has seen 3k+1 or 3k+2 ones, where k is an integer. Example: Input x = 001110111010100100.. Output: 2 = 110011001100000111 Note that the output sequence is delayed by 1 clock cycle compared to the input sequence because the output is a function of the flip-flop outputs. 1.) Draw the Moore state diagram and label the outputs and inputs. Give the meaning of each state. To get full credit, use the minimum number of states. z FSM Notation х SiSolz 001 011- State Meaning "Start" 00 01 111_ 101 10 11 2. Shown below is a 2-bit counter with state S.So that counts the sequence 0, 1, 2, 3,0... When the input Count = 1. When Count = 0, the counter pauses. When both Load = 1 and Count = 1, L1Lo determines the next state. Otherwise, the counter ignores L1L0. Use this counter and no more than 4 gates (NOT, AND, OR, NAND, NOR, XOR, or XNOR) to implement the FSM described at the top of this page. Don't forget input x and output z. L, L. Load Count S, So CLK 2-BIT COUNTER 5