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Question 4: Single Cycle Datapath Control (15 points) We wish to add the support to a pseudo MIPS instruction blt (Branch Less Than) as an I-type pure MIPS instruction in the modified single-cycle datapath below. The encoding of the blt instruction is exactly the same as the beq instruction. It stores the branch target using the PC-relative addressing mode exactly in the same way as the beq instruction, therefore the branch target calculation of blt is identical to that of the beq instruction. The blt instruction compares the values in the rs and rt registers, if the value in rs is strictly less than the value in rt (i.e. R[rs] <R [rt]), it will put the branch target address into PC: PC PC + 4 + BranchAddr Otherwise (i.e. R[rs] >=R [rt]), then: PC PC + 4 Add bit RegOst Branch MemRead MemloReg Instruction [31-26) MemWrite ALUS re RegWrite Instruction [25-21) Read register 1 Read data 1 Instruction [20-16) Read register 2 Registers Read Write register data 2 Address Instruction memory Instruction [15-111 Write data data Data memory Write data 16 Instruction [15-01 Sign axtans extend ALU control Instruction (5.0) a) In the modified datapath, there is a newly added 1-bit control signal called blt, a new output that extract bit 0 from the "ALU result", and an OR gate. All of them are marked in "blue" color. Make proper connections, so that this datapath will support the blt instruction correctly. You are just allowed to make connections to the existing components/wires and add a single gate, but not to expand or add any new MUX or other components. Briefly explain how your modification would support running blt. (7 points) Read address Instruction [31-0] Control ALUOP 32 Shift left 2 ALU Add result Zero SALU ALU result • 3-* - PCSrc Read data
b) Complete the table below for control signals, so that the instructions can be executed correctly. If a control signal is a “don't care”, you must put x, otherwise no mark will be given to it. (8 points) Instr RegDst ALUSrc Mem Reg Mem Mem Branch blt ALU control toReg Write Read Write lw 0 1 1 1 1 0 0 1 0 SW 0 X 01 beq 0 0 0 X blt 0 X X 1 0010