Answer Happy

Create an iteration of the 30-min timer module featuring a
down-counter in Verilog.
1.what are the circuit blocks that will make up your 30 min
timer, ideally presented as a
block diagram sketch
2. how many bits will the down-counter need to implement a 30 min
delay
3. what value must be loaded into the counter at the start of
each cycle in order for the
timer to output the required time expired (t) signal
4. what logic circuit is needed to implement the required time
expired (t) signa
Note:Ignore the true (real world) time of the 30 min timer and
set tclk to any
frequency needed to run a full simulation. Setting tclk in the
range of 2-10GHz seems to work
well (completes needed simulations in less than 1000ns), which you
can do with a combination of
‘timescale settings and tclk period setting in the testbench. We’ll
just have to image that tclk is
1Hz.
30 min timer simulation should show a full cycle of
your timer, staring for loading the start (i.e., reload) value and
counting
down to 0, where output signal, t, should go high. Plus, following
a
complete timer cycle, your simulation should verify that your timer
circuit
will properly reset (clear) and start counting again. You do not
need to show a second full down-
count cycle, but the clear and restart function is critical to
demonstrate. The example below
shows the counter value decreasing by one each cycle (obvious when
you zoom in more) until it
hits 0 and t goes high. Then, the testbench needs to force signal,
ct, to toggle high then low to
start the timer loop over.
Name Value 0 www 0 0 tbcou...0:0] 000 tbtclk ,358.000 ns 1 tbct 1 tbt 360.000 ns w w XXXXXXXXXXXX 36