Answer Happy

Write a testbench on modelsim (software) for
instruction decoder
adder-subtractor register
address register
also, I attached the module file for you so that it will help
you
and don't write it on the page and write it on modelsim properly
and check them by reference module
module instruction_decoderrrl( input [2:01 opcode, input clk, input reg_clr, output oclk, output inc PC, output 1d_MAR, output id_IR, output 1d_ACC, output 1d_Breg, output 1d_out, output [2:01] ld_bus, output mem_wr, output cin, output sum, output tx, output [2:01 I wire clr_sc; //wire [2:0] T; assign clr_sc = (T==3 | reg_clr )? 1: 0; sequence_counter sc (I, oclk, clr_sc); control_block cb (oclk, inc_PC, ld_MAR, 1d_IR, ld_ACC, ld_Breg, ld_out, ld_bus, mem_wr, cin, sum, tx, opcode, I, clk, reg_clr); endmodule module sequence_counter ( output [2:01 sc_out, input clk, input clr }; reg [2:0] count; assign sc_out = count; initial count = 0; always (posedge clk) begin if (clr) count <= 0; else
else endmodule module control_block ( output oclk, output inc_PC, output id_MAR, output 1d_IR, output 1d_ACC, output 1d_Breg, output 1d_out, output [2:0] 1d_bus, output mem_wr, output cin, output sum, output tx, input [2:0] opcode, input [2:01 I, input clk, input reg_clr); reg [12:0] control_vector; reg clk_en; assign (inc_PC, ld_MAR, ld_IR, ld_ACC, ld_Breg, ld_out, ld_bus, mem_wr, cin, sum, tx} = control_vector; assign oclk = clk | (clk_en & ~reg_clr); always @(*) begin. clk_en = 0; case (T) 0: control_vector = 13'b 1_10000_000_0_000; // load MAR with PC. Increment PC 1: control vector = 13'b 0_11000_100_0_000; // load IR with mem [MAR]. Load MAR with address field 2: control vector = 13'b 0 00010 100 0 000; // load B register with the operand end count <= count + 1;
endmodule end case (T) 0: control vector = 13'b 1_10000_000_0_000; // load MAR with PC. Increment PC 1: control vector = 13'b 0_11000_100_0_000; // load IR with mem [MAR]. Load MAR with address field 2: control vector = 13'b 0_00010_100_0_000; // load B register with the operand 3: begin case (opcode) 0: control vector = 13'b 0_00100_011_0_001; // LDA 1: control vector = 13'b 0_00100_011_0_010; // Add 2: control vector = 13'b 0_00100_011_0_000; // Sub 3: control_vector = 13'b 0_00001_011_0_001; // Out 4: begin end default: control_vector = 13'b z_zzzzZ_ZZZ_Z_ZZZ; endcase end default control_vector = 13'b z_zzzzz_zzz_Z_ZZZ; endcase control_vector = 13'b 0_00000_000_0_000; // Hlt control vector has dummy value. setting clk_en to 1 stops the clock clk_en = 1;
module adder_subtractorrl( output [7:0] out_to_bus, output cout, input [7:0] A, input [7:0] B,| input cin, input sum, input tx, input en }; assign (cout, out_to_bus} = (!en)? 9'hzzz : (tx)? B : endmodule (sum) ? A + B + cin: A B + cin;