- All Parts Please 1 (138.82 KiB) Viewed 36 times
All parts please
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answerhappygod
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All parts please
All parts please
Q.3 [Total: 25 marks] The schematic diagram of a TTL logic gate is given below where Vcc = 5V and each transistor is a 3C2BJT1 (datasheet attached). Vcc R3 RB R1 M. w tez D Vi V. R2 w (a) Establish, giving the rationale, the voltages present (with respect to ground) at the base of the four transistors and at the output for the two cases of Vi = 0) and Vi = Vcc. The cut-in voltage and on-voltage can be assumed to be VSyt-in = 0.4V and Von = 0.5V for the diode, D, and Veut-in = 0.6V and VB2 = 7V for each transistor. BE [15 marks] D1 BE (b) Calculate the quiescent current drawn from the supply in both of these cases if power is assumed to be due to the resistive elements and where RB = 4k32, R1 = 1.6 ks2, R2 = 1k2 and R3 = 130$2. [10 marks]
Q.3 [Total: 25 marks] The schematic diagram of a TTL logic gate is given below where Vcc = 5V and each transistor is a 3C2BJT1 (datasheet attached). Vcc R3 RB R1 M. w tez D Vi V. R2 w (a) Establish, giving the rationale, the voltages present (with respect to ground) at the base of the four transistors and at the output for the two cases of Vi = 0) and Vi = Vcc. The cut-in voltage and on-voltage can be assumed to be VSyt-in = 0.4V and Von = 0.5V for the diode, D, and Veut-in = 0.6V and VB2 = 7V for each transistor. BE [15 marks] D1 BE (b) Calculate the quiescent current drawn from the supply in both of these cases if power is assumed to be due to the resistive elements and where RB = 4k32, R1 = 1.6 ks2, R2 = 1k2 and R3 = 130$2. [10 marks]
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