Answer Happy

Problem 2 [50 pts] (a) Design a Verilog code for a 16-bit CSA (Carry Skip Adder) based on the architecture in lecture note. (b) Design a testbench for a 16-bit CSA with an input file which has test inputs. The results should be stored in an output file. First, create an input file (with any editor) called “input.txt" as following binary format (or hex format): 0000111100001111 0101101001011010 1 1111000011110000 1100110000110011 0 The first 16-bit is an input A, the second 16-bit is another input, B, and the last one bit is a carry-in. At least 10 testcases should be in the “input.txt". In your testbench code, you will read “input.txt" to get test input data and create an output file called "output.txt" as following binary format (or hex format): 0 0110100101101010 1 10111101 0010 0011 -... The first 1-bit is a carry-out, and the second 4-bit is the result of adder.