- Zoom Exercise 14 1 Function Binary To Bed A Function That Converts A 12 Bit Vector Representing A 0 To 4095 Integer 1 (37.71 KiB) Viewed 43 times
- Zoom Exercise 14 1 Function Binary To Bed A Function That Converts A 12 Bit Vector Representing A 0 To 4095 Integer 2 (37.71 KiB) Viewed 43 times
- Zoom Exercise 14 1 Function Binary To Bed A Function That Converts A 12 Bit Vector Representing A 0 To 4095 Integer 3 (22.41 KiB) Viewed 43 times
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- Zoom Exercise 14 1 Function Binary To Bed A Function That Converts A 12 Bit Vector Representing A 0 To 4095 Integer 5 (73.13 KiB) Viewed 43 times
- Zoom Exercise 14 1 Function Binary To Bed A Function That Converts A 12 Bit Vector Representing A 0 To 4095 Integer 6 (69.63 KiB) Viewed 43 times
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Exercise 14.7. Function sla for std_ulogic_vector (overloaded operator) a) Write a function that implements the shift left arithmetic (sla) operator for type std_ulogic vector (note in table 9.6 that it does not exist, so this operator will be further overloaded). Locate it in a package and present also a corresponding test circuit (as in example 14.2). You can type the package and the test circuit together, saving that file with the entity's name. b) Show corresponding simulation results.
Name 8000 ns 560.0 ns 1.12 u - Inp Ops 1600 ns320,0 480.0 ms 640,0 XXXXX XOXOX 2 X 3 X 16 17 63 54 X 65 X 128 129 25 outp 5 7 8 Figure 14.1 Simulation results from the code of example 14.2. 1 package subprograms_pkg is function cef1_log2 (input: positive) return natural; end package; 2 3 4 5 6 7 8 9 10 11 12 23 14 15 16 package body subprograms_pkg is function ceil_log2 (input: positive) return natural is variable result: natural -e; begin while 2*result <input loop result result = 1; end loop; return result; end function ceil_log2; end package body; 1 WN use work.subprograms_pkg.all; 2 3 4 5 6 entity test_circuit is generic BITS: natural - 8); port ( inp: in positive range 1 to 2**BITS-1; outp: out natural range e to BITS); end entity; 7 8 9 10 11 12 13 14 15 architecture test_circuit of test_circuit is begin outp < ceil_log2(inp); end architecture; 16
Example 14.3. Function ceil_log2 in an architecture The code below shows the same function of the previous example, now constructed in the declarative region of an architecture (lines 11-13), which is another common place for con- structing functions (though poorer from a reusability perspective). Note that the function is embedded directly in the test circuit, which produces the same results seen in figure 14.1. 1 2 3 5 entity test_circuit is generic BITS: natural :- 8); port ( inp: in positive range 1 to 2**BITS-1; outp: out natural range o to BITS); end entity; 7 8 9 10 11 12 13 architecture test_circuit of test_circuit is function ceil_log2 (inp: positive) return natural is (same as in example 14.2) end function ceil_log2; begin outp <= ceil_log2(inp); end architecture; 14 15 16 17
Name Ops 80.0 ns 160.0 ns 240,0 ns 320,0 ns 400,0 ns 480.0 ns 560,0ns 640,0 4095 99 1234 UU Db 00000000 00000 0100000010010101 0000000010011001 0001001000110100 0915 Figure 14.2 Simulation results from the function of example 14.5. 2 11 12 COSESSION if bcd(15 downto 12) > "100" then bcd(15 downto 12) :: bcd(15 downto 12) + "2011"; end if; if bed (11 downto 8) > "100" then bcd(11 downto 8) :- bed(11 downto 8) + "2011"; end if; if bcd(7 downto 4) > "0100" then bcd(7 downto 4) :- bed(7 downto 4) + "2011"; end if; if bed(3 downto e) > "100" then bcd(3 downto ) :- bed(3 downto ) + "2011"; end if; end loop; bcd :- (bcd(14 downto e) & bin(e)); return std_logic_vector(bcd); end function binary_to_bcd; 20
14.8 Assert and Report Statements The assert and report statements do not infer hardware, which is why they were not studied earlier together with the classical (synthesizable) statements. Instead, assertions are used for checking the design, which is helpful especially for simulation (chapter 18). Assertions can be used in both sequential and concurrent codes. The assert statement [label:) assert condition (report message) (severity level]; A report is generated (displayed on the screen) by the statement above when the assertion is violated (i.e., when the assertion condition is false). Its content (message) can be static or dynamic. In the latter, the to_string function (described ahead) can be used together with the concatenation operator (&) to produce complex, useful messages that combine constant strings with measured/detected values. The severity level can be note (to pass information from the compiler/simulator, with- out design problems), warning (to inform that something unusual was detected, which does not affect the model but can affect its behavior, for example, the inference of unde- sired latches when an incomplete truth table is entered in purely concurrent code), error (to inform that a serious unusual condition was found that does affect the model), or fail- ure (for example, a bug in the design). The default threshold is error; in principle, it should not interrupt compilation or simulation, though the user might be allowed to select the halt condition. For synthesis, it is common to treat error and failure indistinctly, both stop- ping compilation The example below (for simulation) checks whether address is within the allowed range; if not, the message "Unexpected address value. is issued and simulation is interrupted. assert address < 2* *ADDRESS_WIDTH report "Unexpected address value. severity failure; If the report clause is omitted, a default message ("Assertion violation, for example) is exhibited on the screen, as illustrated below: assert address < 2**ADDRESS_WIDTH severity failure; --Reported message: Assertion violation"