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Question 1: Given is a JFET amplifier circuit with rd = 20 k12, IDSS= 10 mA and VP=-8 V. MO The gain of this amplifier where input is at the gate terminal and the output at the drain terminal is i) 3.41 V/V ii) -3.41 V/V iii) -6.0 V/V iv) 6.0 V/V Question 2: For the N-channel MOSFET transistor circuit shown below, the threshold voltage Vuis 0.8V. Neglect channel length modulation effects. When the drain voltage V. -1.6, the drain current I was found to be 0.5 mA. If V, is adjusted to be 2V by changing the values of Rand Vpe the new value of I, (in mA) is (good laboratory exercise) Voo 1) 0.625 mA ii) 0.75 mA iii) 1.125 mA iv) 1.5 mA Question 3: In the CMOS inverter circuit shown below with both MOSFET transistors having k=0.040 mA/V and VTH= 1 V, the current I as shown with arrow in the figure is 10A ii) 0.025 mA pos iin) 0.045 mA iv) 0.090 mA 2.5V 45 NMOS