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Answer questions 2 & 3.
Do Q D Q D2 Q2 CLK C C :: Q, Figure 1 2. Using the asynchronous ripple counter in Figure 1 and assuming that the propagation delay from an input clock to a change in the output of Q is 9ns, what is the worst-case delay (i.e. longest delay) between an input clock pulse and the counter being in a final state. Give which state(s) of the counter have the worst-case delay. 3. If the counter from Problem 2 was synchronous, what would the worst cast propagation delay be?