8 8-bit Adder Subtractor SUB X[7) YO) X(6) YG) X(5) Y45) x4Y4) X3) Y3) X(2) Y(2) xiv 1) xo) YO) SUB FA FA FA FA FAH EL-E

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8 8 Bit Adder Subtractor Sub X 7 Yo X 6 Yg X 5 Y45 X4y4 X3 Y3 X 2 Y 2 Xiv 1 Xo Yo Sub Fa Fa Fa Fa Fah El E 1 (49.51 KiB) Viewed 22 times

8 8-bit Adder Subtractor SUB X[7) YO) X(6) YG) X(5) Y45) x4Y4) X3) Y3) X(2) Y(2) xiv 1) xo) YO) SUB FA FA FA FA FAH EL-ELE - BEHAR FA FA FA D ZIT) Z[6) 215) 2(4) 213) 2/2) 210) 210) Figure 1. 8-bit parallel adder/subtractor 1. Re-design the 8-bit parallel adder/subtractor shown in Figure 1. so it can be used to add/subtract an 8-bit constant K to/from an 8-bit variable X. Each group will re-design the multiplier using the assigned constant K as shown below: Group Constant K 4310 5410 7710 8510 8910 9010 9910 10110 10510 10810 1 2 3 4 5 6 7 8 9 10 2. Write the VHDL code to describe the new 8-bit adder/subtractor design using a suitable design style. 3. Simulate your design and implement it on FPGA. 4. Test your design by connecting its inputs and outputs to the on-board switches and LEDs. respectively.