Design a sequence detector implementing a Moore state machine using three process blocks. The Moore state machine has tw

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Design a sequence detector implementing a Moore state
machine using three process blocks. The Moore state machine has two
inputs (ain[1:0]) and one output (yout). The output yout begins as
0 and remains a constant value unless one of the following input
sequences occurs: (i) The input sequence ain[1:0] = 01, 00 causes
the output to become 0 (ii) The input sequence ain[1:0] = 11, 00
causes the output to become 1 (iii) The input sequence ain[1:0] =
10, 00 causes the output to toggle. Develop a testbench (similar to
the waveform shown below) and verify the model through a behavioral
simulation. Use SW15 as the clock input, SW1- SW0 as the ain[1:0]
input, the BTNU button as reset input to the circuit, and LED0 as
the yout output. Go through the design flow, generate the
bitstream, and download it into the Nexys4 board. Verify the
functionality. See simulation picture(sequence detector simulation)
in folder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity pattern_decoder is
Port (
clk : IN std_logic;
reset : IN std_logic;
ain : IN STD_LOGIC_vector(1 downto
0);
flag : OUT std_logic );
end pattern_decoder;
architecture Behavioral of pattern_decoder is
type state_type is (S0, S1, S2, S3);
signal state, next_state : state_type;
begin
SYNC_PROC : process (clk)
begin
if rising_edge(clk) then
if (reset = '1')
then

state <= S0;
else
state <=
next_state;
end if;
end if;
end process;
OUTPUT_DECODE : process (state)
begin
case (state) is
when S0 =>
when S1 =>
when S2 =>
when S3 =>
when others
=>
end case;
end process;
NEXT_STATE_DECODE : process (state, ain)
begin
next_state <= S0;
case (state) is
when S0 =>
when S1 =>
when S2 =>

when S3 =>

when others =>
end case;
end process;
end Behavioral;
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