8 Consider The Legv8 Code Below Assume That X1 Is Initialized To 11 And X2 Is Initialized To 22 Addi X1 X2 5 Add X 1 (154.82 KiB) Viewed 39 times
8. Consider the LEGv8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) What would the final values of registers X3 and X4 be if the above instructions are executed in a pipeline processor that does not handle data hazards (i.e., does not stall the pipeline or use data forwarding for data hazards)? (b) What would the final values of register X5 be if the above instructions are executed in a pipeline processor that does not handle data hazards (i.e., does not stall the pipeline or use data forwarding for data hazards)? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (C) Suppose you executed the code on a version of the pipeline from Section 4.5 that handles data hazards by simply stalling the pipeline (i.e. inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed.
ADDI X1, X2, #5 IF ID EX MEM WB ADD X3, X1, X2 > ADDI X4, X1, #15 ADD X5, X1, X1 (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: IF ID EX MEM WB ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2
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