- 6 Problems In This Exercise Assume That The Logic Blocks Used To Implement A Processor S Datapath Have The Following La 1 (518.61 KiB) Viewed 44 times
6. Problems in this exercise assume that the logic blocks used to implement a processor's datapath have the following la
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6. Problems in this exercise assume that the logic blocks used to implement a processor's datapath have the following la
6. Problems in this exercise assume that the logic blocks used to implement a processor's datapath have the following latencies: I-Mem/ Register D-Mem File $ Sign extend Control Mux Single Register gate Read 5ps ALU Adder 250ps 150 ps 25 ps 200 ps 150 ps 30 ps 50ps 50ps “Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. (a) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (b) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (c) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of B? (e)What is the minimum clock period for this CPU?
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