In a small signal differential gain vs input CM level graph, the gain decreases after V2 due to:

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a) As the input voltage increases, the output will be clipped
b) When the input voltage to the transistors are high, the transistor enters saturation region and increases the current, which inturn decreases the output voltage = VDD – Rd.Iss
c) When Common Mode voltage is greater than or equal to V2, the input transistors enter triode region, the gain begins to fall
d) Increasing the input voltage beyond V2 causes the gate oxide to conduct and the gain is reduced