- B C Question 3 A Microprocessor Comprising Of Instruction Fetch If Instruction Decode Id Execution Ex Memor 1 (110.63 KiB) Viewed 34 times
(b) (c) Question 3 A microprocessor comprising of instruction fetch (IF), instruction decode (ID), execution (EX), memory (MEM) and write back (WB) stages are going to be designed to execute the following MIPS program. (a) add (0) or and sub $5, $3, $1 $6, $2, $8 $3, $5, $4 $7 $1 $9 Show the execution of this program on an instruction-time if the program is to be executed on: a single clock cycle microprocessor. a multi clock cycle microprocessor. a 5-stage pipelined microprocessor. (4 marks) (4 marks) (4 marks) Determine the type of a pipeline hazard with reason in the execution of this program. (4 marks) Suggest a solution for the problem in (b) without an addition of circuitry in the microprocessor. (4 marks) [20 marks]